1. Field of the Invention
The present invention relates to a semiconductor device such as a field effect transistor used as, for example, a high-frequency power amplifying device.
2. Description of the Related Art
In recent years, with advance in power of a high-frequency semiconductor element, high frequency characteristics and reliability in a field effect transistor (to be referred to as a Field Effect Transistor: abbreviated as an FET hereinafter) are required to be improved.
In general, in GaAs-FET, by a method of connecting a source electrode to a ground electrode through a via hole, a reduction in source inductance is achieved.
For example, in Japanese Patent Application Laid-Open No. 2004-55869, as shown in FIG. 1(b), thereof a via hole 116 reaching a source electrode 112 from a rear surface side of a semiconductor substrate 111 having a main surface on which the source electrode 112, a gate electrode 113, and a drain electrode 114 are formed. The source electrode 112 is grounded by a gold plating layer 115 formed inside the via hole 116 and the rear surface of the semiconductor substrate 111.
In this manner, each source electrode is connected through a via hole to make it possible to reduce a source inductance. Furthermore, since mechanical strength is deteriorated by forming the via hole, in order to improve mechanical strength against vertical stress, a method of shifting positions of via holes from each other is proposed.
However, in recent years, a semiconductor substrate used in the FET is thinned to have approximately several ten micrometers in consideration of an aspect ratio of a via hole and heat-radiation characteristics of the FET. Furthermore, a metal thickness of a ground electrode increases, in the above method, the vertical stress cannot be sufficiently moderated, and deterioration of handling performance, a decrease in yield caused by cracking of an FET chip, cannot be easily suppressed.